onsemi’s Embedded Power Platform (EPP) is a packaging architecture change, not a new place to drop a voltage regulator. The distinctive move is to embed multiple dies in a silicon-based structure and replace wire bonds with wafer-level redistribution layers. That pulls part of the power-module current path into a fabrication-controlled interconnect.

Semiconductor Today’s September 18 coverage follows onsemi’s September 16 announcement. The engineering question is specific: what has to be demonstrated when a power-current path leaves discrete package connections and moves onto patterned wafer-level routing?

Do not collapse this into vertical power delivery under an accelerator. Vertical delivery is about where the final supply path sits and how much impedance it carries. EPP is about how a power assembly is built—and that assembly may serve several applications. The two ideas are related in the AI-power conversation. They are not synonyms.

What onsemi has actually disclosed about EPP

The EPP technology page describes embedded semiconductor devices linked by redistribution layers, or RDLs. It also describes integrating switching, control, drive, and isolation functions on the platform, with support for silicon, silicon carbide, and gallium nitride.

The September 16 announcement says EPP uses onsemi’s existing 12-inch silicon manufacturing. Subaru is named as an early evaluation partner. Sampling is expected to begin in 2026. Those are platform and engagement disclosures. They are not evidence that a named production vehicle, or a broadly available catalog module, already uses EPP.

Support for several semiconductor materials also does not mean every device is fabricated monolithically in one process. The disclosed approach is multi-die integration. Buyers should ask which combinations have been implemented, characterized, and qualified. A platform’s technology coverage is not a product specification.

DisclosedNot disclosed
Embedded dies linked by wafer-level RDLsNamed production vehicle already using EPP
Switching, control, drive, and isolation as integration targetsWhich die combinations are characterized and qualified
Si, SiC, and GaN technology supportA universal density specification for every combination
Existing 12-inch silicon manufacturingFull thermal boundary conditions for a finished system
Subaru as an early evaluation partner; sampling expected in 2026Catalog availability or a shipping production module

Why replacing wire bonds with RDLs changes the electrical problem

A redistribution layer is patterned conductive routing. It connects device terminals to package interfaces. Replacing a raised wire with a planar route changes the geometry a designer can control. Current paths can be laid out more deliberately. The routing stack also becomes part of the power-device specification, not an afterthought of assembly.

The following is engineering analysis, not a reported EPP test result. During a fast current transition, parasitic inductance contributes a voltage V = L × di/dt. Lower commutation-loop inductance can therefore cut overshoot at the same current slew rate. The relevant loop includes outgoing and return paths. A connection that looks short in a photograph is not, by itself, evidence of low loop inductance.

An evaluation team should hold bus voltage, current, device generation, gate-drive conditions, and temperature constant. Measurements should separate package-terminal behavior from the rest of the test fixture. Otherwise an “improvement” attributed to EPP may partly be a different board layout or a different switching speed.

Reliability questions shift from bonds to the full stack

The useful question is no longer only whether individual wire bonds survive. It is how the complete embedded-die and RDL stack behaves. A sensible evidence request includes routing resistance, allowable current, dielectric isolation, interface integrity, and how those properties move after stress.

That is not a claim that EPP has a particular failure mode. It is a qualification agenda for a different construction. Engineers need to know where losses occur, which interfaces set operating limits, and how manufacturing variation enters the model.

Using silicon as the structural platform also does not set the temperature of the finished system. Heat still crosses interfaces and enters a cooling arrangement. A package comparison should state the cooling boundary conditions, dissipated power, and temperature measurement location. Lower case temperature, lower junction temperature, and lower thermal resistance answer different questions.

How to read the 3–5× power-density claim

onsemi’s announcement presents a three-to-fivefold power-density claim depending on application. The technology page separately highlights up to fourfold improvement. Do not mash those headlines into one universal EPP specification, and do not treat them as guaranteed gains for every device combination.

Before a density number enters a design decision, fix the denominator. Is density measured against package volume, converter volume, board area, or an assembly that includes cooling? Also fix the reference design and the operating duty. A smaller package can be useful without shrinking the complete system by the same factor.

The same discipline applies to development speed. A faster platform design cycle is not automatically a shorter customer qualification cycle. Electrical characterization, application validation, and release approval still have their own evidence requirements.

A practical evaluation sequence for EPP samples

For teams considering the platform, four work packages would make an early engagement more decision-ready:

  1. Define the construction. Request a package cross-section, terminal map, routing-stack description, and supported die combinations for the proposed implementation.
  2. Correlate electrical models. Compare extracted parasitics with measured switching behavior across agreed operating conditions.
  3. Close thermal and isolation boundaries. Document the cooling interface, temperature limits, insulation requirements, and relevant test conditions.
  4. Separate milestones. Track engineering samples, characterization, customer qualification, and production release independently.

Those steps keep the conversation on evidence. They also prevent a density headline from substituting for a correlated package model.

The takeaway

EPP’s distinctive proposition is a wafer-level interconnect and integration route for power systems. Its value will be established by measured improvements under matched conditions and by a qualified construction—not by treating a package announcement as a finished system specification.

The next useful deliverable is a correlated package model plus application-specific sample data. That would let customers evaluate the new current path on engineering evidence rather than on a density headline alone.

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